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PM73122 AAL1gatorTM-32 32 Link CES/DBCES AAL1 SAR
FEATURES
* Supports 32 structured/unstructured T1, E1, or two unstructured DS3, E3 or STS-1/STM-0 links over ATM. * Compliant with ATM Forum's CES (AFVTOA-0078), and ITU-T I.363.1. * Supports up to 1024 VCs. * Supports n x 64 (consecutive channels) and m x 64 (nonconsecutive channels) structured data format with channel associated signaling (CAS) support. * Internal E1/T1 clock synthesizers provided for each line which can be controlled via internal synchronous residual time stamp (SRTS) or an internal programmable weighted moving average adaptive clocking algorithm in unstructured mode. Clock synthesizers can also be controlled externally to provide customization of SRTS or adaptive clocking methods. * Provides transparent transmission of CCS and CAS and termination of CAS signaling. * Compliant with ATM Forum's Dynamic Bandwidth Circuit Emulation Service (DBCES) AF-VTOA-0085. Supports idle channel detection via processor intervention, CAS signaling, or data pattern detection. Provides idle channel indication on a per channel basis. * Supports AAL0 mode, selectable on a per VC basis. * Provides transmit and receive buffers which can be used for OAM cells as well as any other user-generated cells such as AAL5 cells for ATM signaling.
UTOPIA INTERFACE
* Supports 52 MHz, 8/16-bit Level 2, Multi-Phy Mode (MPHY) with parity, 8/16-bit Level 1, SPHY and 8-bit Level 1, ATM Master modes. * The receive UTOPIA port can be configured as a single PHY or as four separate PHYs. * Provides an optional 8/16-bit AnyPHYTM slave interface. * Provides a three cell FIFO for UTOPIA loopback support on a per VC basis or a global basis.
TRANSMIT SECTION
* Provides individually enabled per-VC data and signaling conditioning in the transmit cell direction and per DS0 data and signaling conditioning in the transmit line direction. Includes DS3 AIS conditioning support in both directions.
* Provides per-VC configuration of time slots allocated, CAS support, partial cell size, data and signaling conditioning, ATM Cell header definition. * Generates AAL1 sequence numbers, pointers and SRTS values in accordance with ITU-T I.363.1. Multicast connections are supported. * Provides a patented frame based calendar queue service algorithm with anti-clumping add-queue mechanism that produces minimal CDV. In unstructured mode uses non-frame based scheduling to optimize CDV. * Queues are added by making entries into an add queue FIFO to minimize queue activation overhead.
BLOCK DIAGRAM
RL_CLK[15:0] TL_CLK[15:0] TL_CLK_OE RAM2_WEB[1:0] RAM2_PAR[1:0] RAM2_ADSCB RAM2_D[15:0] RAM2_A[17:0] CRL_CLK CTL_CLK SYSCLK NCLK RAM2_OEB RAM2_CSB
Line Interface
LINE_MODE[1:0]
Clock MUX
RSTB SCAN_ENB SCAN_MODEB TATM_DATA[15:0] TATM_PAR TATM_ENB TATM_SOC TATM_CLAV TATM_CLK RPHY_ADD[4:0] RATM_DATA[15:0] RATM_PAR RATM_ENB RATM_SOC RATM_CLAV RATM_CLK TPHY_ADD[4:0] 8 8 8
RAM2 Interface
ADETECT AACTIVE REFCLK C1FP 32 8 DDATA[7:0]
A1SP
19.44 MHz SBI Interface
DDP DPL DV5 ADATA[7:0] ADP AJUST_REQ APL AV5
8
32
A1SP UTOPIA Interface
8 8
LINE INTERFACE
* Supports the following flexible line interfaces: * 32 T1, E1 or 2 DS3 links using the 19.44 MHz Scalable Bandwidth Interconnect (SBITM) bus. Can map any SBI tributary to any of the 32 AAL1 links. * 16 individual T1 or E1 lines. * Eight H-MVIP lines at 8 MHz. * Two unstructured DS3, E3 or STS1/STM-0 lines. * Provides lineside loopback support on a per channel basis.
32
F0B
H-MVIP
16
8 TL_DATA[15:0]
A1SP Low Speed High Speed
16
TL_SYNC[15:0] TL_SIG[15:0] RL_DATA[15:0] RL_SYNC[15:0] RL_SIG[15:0]
8
2
A1SP
2
JTAG
RAM 1 Interface
Processor Interface
External Clock Interface
RAM1_ADSCB
CGC_DOUT[3:0]
D[15:0]
A[19:0]
TRST
CGC_VALID
RAM1_PAR[1:0]
RAM1_D[15:0]
RAM1_WEB[1:0]
RAM1_A[17:0]
PMC-1991271 (r2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
Copyright PMC-Sierra, Inc. 2001
CGC_LINE[4:0]
CGC_SER_D
RAM1_CSB
ACKB
ADAP_STB
RDB
CSB
RAM1_OEB
SRTS_STB
TMS
TCK
TDI
WRB
TDO
ALE
INTB
PM73122 AAL1gatorTM-32 32 Link CES/DBCES AAL1 SAR
RECEIVE SECTION
* Provides per-VC configuration of time slots allocated, partial cell size, sequence number processing options, cell delay variation tolerance buffer depth, maximum buffer depth. * Supports Fast Sequence Number processing and Robust Sequence Number processing. * Provides single maskable, opencollector interrupt with master interrupt register to facilitate processing for AAL1, RAM, UTOPIA and SBI exceptions. * Provides multiple counters in the Cell Transmit and Receive directions as required by the ATM Forum's CES-IS 2.0 MIB. * Provides a seamless interface to two external 256K x 16(18) (10 ns) Synchronous SRAMs or ZBT RAMs. * Low-power 2.5V CMOS with 3.3V, 5V tolerant I/O. * 352-pin super ball grid array (SBGA) package.
APPLICATIONS
* Multiservice Switch CES Port Cards. * DACS with an ATM interface. * Optical Line Termination in an ATM Passive Optical Network (APON) System.
GENERAL
* Provides a microprocessor interface for configuration, management, and statistics gathering.
TYPICAL APPLICATIONS
ATM MULTISERVICE SWITCH
TelecomBus SBI Any-PHY (Packet) UTOPIA L2/ Any-PHY (Cell)
PM8316 TEMUX-84
PM7385 FREEDM84A672
Packet/Cell Internetworking Function
PM8316 TEMUX-84 PM5313 SPECTRA622 PM8316 TEMUX-84
PM7341 S/UNI-IMA84
Any-PHY
APPI
PM7326 S/UNI-APEX
OC-12
PM73122 PM73122 AAL1gatorPM73122 AAL1gator32 AAL1gator32 32
PM7324 S/UNIATLAS
PM8316 TEMUX-84
SBI to H-MVIP
VoATM DSP
DACS WITH AN ATM INTERFACE
H-MVIP UTOPIA L2/ Any-PHY UTOPIA L2
PM73122 AAL1gator-32 TDM Switch
PM7328 S/UNI-ATLAS1K800 PM5384 S/UNI-1x155
PM73122 AAL1gator-32
PM7329 S/UNI-APEX1K800
Head Office: PMC-Sierra, Inc. 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200
To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator
All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PMC-1991271 (r2) Copyright PMC-Sierra, Inc. 2001. All rights reserved. August 2001. S/UNI is a registered trademark and AAL1gator-32, AnyPHY, SBI, TEMUX-84, FREEDM84A672 and PMC-Sierra are trademarks of PMC-Sierra, Inc.

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